Garo Bournoutian

E-mail:
Phone: (858) 822-2505
Office: EBU3b 2142
Website: garo.ucsd.edu

Research Area(s): Dynamic Embedded Computer Architectures based on Application-Specific Information.

C.V./Resume: Unavailable

Education:

• Ph.D. in Computer Engineering. University of California, San Diego. 2007 - Present.
• C.Phil. in Computer Engineering. University of California, San Diego. 2007 - 2009.
• M.S. in Computer Science. University of California, San Diego. 2005 - 2007.
• B.S. in Computer Engineering. University of California, San Diego. 2000 - 2005.
• B.S. in Cognitive Neuroscience. University of California, San Diego. 2000 - 2005.

Journal Publications:

• G. Bournoutian and A. Orailoglu, "Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions," Design Automation for Embedded Systems (DAEM), pp. 1-18, 2010. [ DOI 10.1007/s10617-010-9058-y ]

Conference Publications:

• G. Bournoutian and A. Orailoglu, "Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors" Proc. of the Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 89-98, 2011. [ pdf ]
• G. Bournoutian and A. Orailoglu, "Dynamic, non-linear cache architecture for power-sensitive mobile processors" Proc. of the Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 187-194, 2010. [ pdf ]
• G. Bournoutian and A. Orailoglu, "Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions," Proc. of the Int'l Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 117-126, 2009. [ pdf ]
• G. Bournoutian and A. Orailoglu, "Miss reduction in embedded processors through dynamic, power-friendly cache design," Proc. of the 45th Design Automation Conference (DAC), pp. 304-309, 2008. [ pdf ]

Teaching:

• CSE 131 - Compiler Construction. Summer 2011